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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM72F6/D
512KB and 1MB Synchronous Fast Static RAM Module
The MCM72F6 (512KB) is configured as 64K x 72 bits and the MCM72F7 (1MB) is configured as 128K x 72 bits. Both are packaged in a 168-pin dual- in-line memory module DIMM. Each module uses Motorola's 3.3 V 64K x 18 bit flow-through BurstRAMs. Address (A), data inputs (DQ, DP), and all control signals except output enable (G) are clock (K) controlled through positive-edge-triggered noninverting registers. Write cycles are internally self-timed and initiated by the rising edge of the clock (K) input. This feature provides increased timing flexibility for incoming signals. Synchronous byte write (W) allows writes to either individual bytes or to both bytes. * * * * * * * * Single 3.3 V + 10%, - 5% Power Supply Plug and Pin Compatibility with 2MB and 4MB Multiple Clock Pins for Reduced Loading All Inputs and Outputs are LVTTL Compatible Byte Write Capability Fast SRAM Access Times: 9/10/12 ns Decoupling Capacitors for Each Fast Static RAM High Quality Multi-Layer FR4 PWB With Separate Power and Ground Planes * Amp Connector, Part Number: 390064-4 * 168-Pin DIMM Module
MCM72F6 MCM72F7
168-LEAD DIMM CASE 1115J-01 TOP VIEW
1
11
40 41
84
REV 3 11/24/97
(c) Motorola, Inc. 1997 MOTOROLA FAST SRAM
MCM72F6*MCM72F7 1
MCM72F6 BLOCK DIAGRAM
64K x 18 SE1 G A0 - A15 ADSC SBa SBb K SE2 ADV ADSP SGW SW LBO SE3 DQa0 - DQa7 DQa8 DQb0 - DQb7 DQb8 64K x 18 SE1 G A0 - A15 ADSC SBa SBb K SE2 ADV ADSP SGW SW LBO SE3 DQa0 - DQa7 DQa8 DQb0 - DQb7 DQb8 64K x 18 SE1 G A0 - A15 ADSC SBa SBb K SE2 ADV ADSP SGW SW LBO SE3 DQa0 - DQa7 DQa8 DQb0 - DQb7 DQb8 64K x 18 SE1 G A0 - A15 ADSC SBa SBb K SE2 ADV ADSP SGW SW LBO SE3 DQa0 - DQa7 DQa8 DQb0 - DQb7 DQb8
E0 G0 A0 - A15 ADSP W0 W1 K0
W2 W3 K1
W4 W5 K2
W6 W7 K3
VDD
VSS
DQ0 - DQ7 DP0 DQ8 - DQ15 DP1
DQ16 - DQ23 DP2 DQ24 - DQ31 DP3
DQ32 - DQ39 DP4 DQ40 - DQ47 DP5
DQ48 - DQ55 DP6 DQ56 - DQ63 DP7
MCM72F6*MCM72F7 2
MOTOROLA FAST SRAM
MCM72F7 BLOCK DIAGRAM
64K x 18 SE1 G A0 - A15 ADSC SBa SBb K DQa0 - DQa7 DQa8 DQb0 - DQb7 DQb8 SE2 ADV ADSP SGW SW LBO SE3 64K x 18 SE1 G A0 - A15 ADSC SBa SBb K DQa0 - DQa7 DQa8 DQb0 - DQb7 DQb8 SE2 ADV ADSP SGW SW LBO SE3 64K x 18 SE1 G A0 - A15 ADSC SBa SBb K DQa0 - DQa7 DQa8 DQb0 - DQb7 DQb8 SE2 ADV ADSP SGW SW LBO SE3 64K x 18 SE1 G A0 - A15 ADSC SBa SBb K DQa0 - DQa7 DQa8 DQb0 - DQb7 DQb8 SE2 ADV ADSP SGW SW LBO SE3
E0 G0 A0 - A15 ADSP W0 W1 K0
W2 W3 K1
W4 W5 K2
W6 W7 K3
VDD
VSS
DQ0 - DQ7 DP0 DQ8 - DQ15 DP1
DQ16 - DQ23 DP2 DQ24 - DQ31 DP3
DQ32 - DQ39 DP4 DQ40 - DQ47 DP5
DQ48 - DQ55 DP6 DQ56 - DQ63 DP7
VDD
VSS E1 G1
64K x 18 A0 - A15 ADSC SBa SBb K DQb8 DQb0 - DQb7 DQa8 DQa0 - DQa7 SE2 ADV ADSP SGW SW LBO SE3 SE1 G
64K x 18 A0 - A15 ADSC SBa SBb K DQb8 DQb0 - DQb7 DQa8 DQa0 - DQa7 SE2 ADV ADSP SGW SW LBO SE3 SE1 G
64K x 18 A0 - A15 ADSC SBa SBb K DQb8 DQb0 - DQb7 DQa8 DQa0 - DQa7 SE2 ADV ADSP SGW SW LBO SE3 SE1 G
64K x 18 A0 - A15 ADSC SBa SBb K DQb8 DQb0 - DQb7 DQa8 DQa0 - DQa7 SE2 ADV ADSP SGW SW LBO SE3 SE1 G
MOTOROLA FAST SRAM
MCM72F6*MCM72F7 3
PIN ASSIGNMENT 168-LEAD DIMM TOP VIEW
VSS DQ63 DQ62 VDD DQ60 DQ58 VSS DQ56 DQ55 VSS DQ53 DQ51 VSS DQ49 DP5 VDD DQ46 DQ44 VSS DQ42 DQ40 VSS DQ39 DQ37 VSS DQ35 DQ33 VSS K3 VSS DP3 DQ30 VDD DQ28 DQ26 VSS DQ24 DQ23 VSS DQ21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 VSS DP7 DQ61 VSS DQ59 DQ57 VSS DP6 DQ54 VDD DQ52 DQ50 VSS DQ48 DQ47 VSS DQ45 DQ43 VSS DQ41 DP4 VDD DQ38 DQ36 VSS DQ34 DQ32 VSS K2 VSS DQ31 DQ29 VSS DQ27 DQ25 VSS DP2 DQ22 VDD DQ20
DQ19 VSS DQ17 DP1 VDD DQ14 DQ12 VSS DQ10 DQ8 VSS DQ7 DQ5 VSS DQ3 DQ1 VDD NC NC VSS NC A14 VSS A12 A10 VSS A8 A6 VDD A4 A2 A0 VSS K1 VSS W7 W5 VSS W3 W1 VSS G1 E1 VSS
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
DQ18 VSS DQ16 DQ15 VSS DQ13 DQ11 VSS DQ9 DP0 VDD DQ6 DQ4 VSS DQ2 DQ0 VSS NC NC VSS A15 A13 VDD A11 A9 VSS A7 A5 VSS A3 A1 ADSP VSS K0 VSS W6 W4 VSS W2 W0 VDD G0 E0 VSS
MCM72F6*MCM72F7 4
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations 62, 64, 65, 67, 68, 70, 71, 72, 145, 146, 148, 149, 151, 152, 154, 155 156 15, 31, 44, 86, 92, 105, 121, 134 2, 3, 5, 6, 8, 9, 11, 12, 14, 17, 18, 20, 21, 23, 24, 26, 27, 32, 34, 35, 37, 38, 40, 41, 43, 46, 47, 49, 50, 52, 53, 55, 56, 87, 89, 90, 93, 95, 96, 98, 99, 101, 102, 104, 107, 108, 110, 111, 115, 116, 118, 119, 122, 124, 125, 127, 128, 130, 131, 133, 136, 137, 139, 140 167, 83 Symbol A0 - A15 Type Input Description Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Addresss Status Controller: Initiates read, write, or chip deselect cycle. Synchronous Parity Data Inputs/Outputs. I/O Synchronous Data Inputs/Outputs.
ADSP DP0 - DP7 DQ0 - DQ63
Input
E0, E1
Input
Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. E1 is only used on 1MB module. Asynchronous Output Enable Input: Low -- enables output buffer. High -- DQx pins are high impedance. G1 is only used on 1MB module. Clock: This signal registers the address, data in, and all control signals except G and LBO. Synchronous Byte Write Inputs: x refers to the byte being written (byte a, b). SGW overrides SBx. Power Supply: 3.3 V + 10%, - 5%. Must be connected on all modules. Ground.
166, 82
G0, G1
Input
29, 74, 113, 158 76, 77, 79, 80, 160, 161, 163, 164 4, 16, 33, 45, 57, 69, 94, 106, 123, 135, 147, 165 1, 7, 10, 13, 19, 22, 25, 28, 30, 36, 39, 42, 48, 51, 54, 60, 63, 66, 73, 75, 78, 81, 84, 85, 88, 91, 97, 100, 103, 109, 112, 114, 117, 120, 126, 129, 132, 138, 141, 144, 150, 153, 157, 159, 162, 168 58, 59, 61, 142, 143
K0 - K3 W0 - W7 VDD VSS
Input Input Supply Supply
NC
No Connection: There is no connection to the chip.
DATA RAM MCM69F618A SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, 3 and 4)
Next Cycle Deselect Begin Read Read Read Begin Write Write Address Used None External Address Current Current External Current E 1 0 X X 0 X ADSP 0 0 1 1 0 1 G X 0 1 0 X X DQx High-Z DQ High-Z DQ High-Z High-Z WRITE X Read Read Read Write Write
NOTES: 1. X = don't care, 1 = logic high, 0 = logic low. 2. Write is defined as any Wx low. 3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low. 4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times.
MOTOROLA FAST SRAM
MCM72F6*MCM72F7 5
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating Power Supply Voltage Voltage Relative to VSS Output Current (per I/O) Power Dissipation Ambient Temperature Die Temperature Temperature Under Bias MCM72F6 MCM72F7 Symbol VDD Vin, Vout Iout PD TA TJ Tbias Value - 0.5 to + 4.6 - 0.5 to VDD + 0.5 20 4.6 9.2 0 to 70 110 - 10 to + 85 Unit V V mA W C C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Storage Temperature Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, - 5%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL - 2.0 V for t tKHKH/2. Symbol VDD VIH VIL Min 3.135 2.0 - 0.5* Max 3.6 VDD + 0.3 0.8 Unit V V V
DC CHARACTERISTICS
Parameter Input Leakage Current (0 V Vin VDD) Output Leakage Current (0 V Vin VDD) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) VOL VOH Min -- -- -- 2.4 Max 1.0 1.0 0.4 -- Unit A A V V
POWER SUPPLY CURRENTS
Parameter AC Supply Current (Device Selected, All Outputs Open, Cycle Time tKHKH min) MCM72F6DG9 MCM72F6DG10 MCM72F6DG12 MCM72F7DG9 MCM72F7DG10 MCM72F7DG12 MCM72F6DG9 MCM72F6DG10 MCM72F6DG12 MCM72F7DG9 MCM72F7DG10 MCM72F7DG912 MCM72F6DG9 MCM72F6DG10/12 MCM72F7DG9 MCM72F7DG10/12 Symbol IDDA Min -- Max 900 860 840 1800 1720 1680 440 400 380 880 800 760 160 140 320 280 Unit mA
CMOS Standby Supply Current (Deselected, Clock (K) Cycle Time tKHKH, All Inputs Toggling at CMOS Levels Vin VSS + 0.2 V or VDD - 0.2 V)
ISB1
--
mA
Clock Running Supply Current (Deselected, Clock (K) Cycle Time tKHKH, All Other Inputs Held to Static CMOS Levels Vin VSS + 0.2 V or VDD - 0.2 V)
ISB2
--
mA
MCM72F6 CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance I/O Capacitance W, K Other Inputs Symbol Cin CI/O Typ -- -- -- Max 16 36 19 Unit pF pF
MCM72F6*MCM72F7 6
MOTOROLA FAST SRAM
MCM72F7 CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70 C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance W, K E, G Other Inputs Symbol Cin Typ -- -- -- -- Max 22 36 60 28 Unit pF
I/O Capacitance
CI/O
pF
MASS (Periodically Sampled Rather Than 100% Tested)
Parameter MCM72F6 MCM72F7 Max 16 20 Unit g g
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, - 5%, TA = 0 to 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20 to 80%) Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3 and 4)
MCM72F6-9 MCM72F7-9 Parameter P Cycle Time Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q-High-Z Clock High to Q-High-Z Clock High Pulse Width Clock Low Pulse Width Setup Times Address ADSP Data In Write Chip Enable Address ADSP, ADSC, ADV Data In Write Chip Enable Symbol S bl tKHKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tKHKL tKLKH tAVKH tADKH tDVKH tWVKH tEVKH tKHAX tKHADX tKHDX tKHWX tKHEX Min 12 -- -- 0 3 0 -- 3 4 4 2.5 Max -- 9 5 -- -- -- 5 5 -- -- -- MCM72F6-10 MCM72F7-10 Min 15 -- -- 0 3 0 -- 3 5 5 2.5 Max -- 10 5 -- -- -- 5 5 -- -- -- MCM72F6-12 MCM72F7-12 Min 16.6 -- -- 0 3 0 -- 3 6 6 2.5 Max -- 12 6 -- -- -- 6 6 -- -- -- Unit Ui ns ns ns ns ns ns ns ns ns ns ns 5 5 5 5, 6 5, 6 Notes N
Hold Times:
0.5
--
0.5
--
0.5
--
ns
NOTES: 1. In setup and hold times, write refers to either any SBx and SW or SGW is low. 2. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted. 3. All read and write cycle timings are referenced from K or G. 4. G is a don't care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle. 5. This parameter is sampled and not 100% tested. 6. Measured at 200 mV from steady state.
MOTOROLA FAST SRAM
MCM72F6*MCM72F7 7
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Z0 = 50 OUTPUT 50 VL = 1.5 V
Figure 1. AC Test Load
READ/WRITE CYCLES
t KHKH K t KHKL t KLKH
Ax
A
B
C
D
E
F
G
ADSP
E
W
G t KHQV DQx t KHQZ DESELECTED Q(n) Q(A) t KHQX1 READ WRITES Q(B) t KHQX2 Q(C) t GHQZ D(D) D(E) D(F) t GLQX READ t GLQV Q(G)
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
72F
X
XX
XX
Speed (9 = 9 ns, 10 = 10 ns, 12 = 12 ns) Package (DG = Gold Pad DIMM) Memory Size (6 = 512KB, 7 = 1 MB)
Full Part Numbers -- MCM72F6DG9 MCM72F7DG9
MCM72F6DG10 MCM72F7DG10
MCM72F6DG12 MCM72F7DG12
MCM72F6*MCM72F7 8
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
168-LEAD DIMM CASE 1115J-01 D1 0.15 (0.006) D5 C L
COMPONENT AREA
M
ABC
(DATUM PLANE C)
E
A
A
VIEW D
1
VIEW D
MOTOROLA FAST SRAM
EEEEEEEEEEEEEEE EEEEEEE EEEEEEE EEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEE EEEE EEEEEE EEEE E EEEEEE EEEEE E EEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEE
1 84 10 11
A1
NOTE 4
VIEW C D4 D3
40
41
D6 D4
VIEW B
E2
NOTE 5
E1
NOTE 6
D2 /2 D2 FRONT VIEW
94 85 95
VIEW C B SIDE VIEW
168
0.016 (0.4)
M
EEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEE EE EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEE EEEE EEEEEE EEEE E EEEEEE EEEEE E EEEEEE EEEEEEE E
COMPONENT AREA
BACK VIEW
R
R
K 0.004 (0.1)
M
ABC
VIEW A
168X
M
ABC
168X
L1
168X
L
162X
e
E E E E E E EE EE EEEE EEEE EEEE EEEE EEEE
b 0.004 (0.1)
R
VIEW C
EE E E EE EE EE
K 0.004 (0.1)
M
A5
A5
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCH. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS E AND A1 DEFINE A DOUBLE-SIDED MODULE. 5. DIMENSION E2 DEFINES OPTIONAL SINGLE-SIDED MODULE 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. 7. D5 DIMENSION DEFINES SLOT END AND EDGE OF COMPONENT AREA. INCHES MIN MAX 1.095 1.105 0.390 --- 0.118 BSC 0.700 BSC 0.154 0.161 0.118 0.128 0.037 0.041 5.245 5.255 5.014 BSC 1.700 BSC 0.250 BSC 0.118 --- 0.125 BSC 0.050 BSC --- 0.200 0.046 0.054 --- 0.148 0.075 0.083 0.100 --- --- 0.010 0.114 0.122 MILLIMETERS MIN MAX 27.81 28.07 9.90 --- 3.00 BSC 17.78 BSC 3.90 4.10 3.00 3.25 0.95 1.05 133.22 133.48 127.35 BSC 43.18 BSC 6.35 BSC 3.00 --- 3.175 BSC 1.27 BSC --- 4.00 1.17 1.37 --- 2.70 1.90 2.10 2.54 --- --- 0.25 2.90 3.10
EE E EE EE EE E EE EEE E E EEE E E
C
DIM A A1 A2 A3 A4 A5 b D1 D2 D3 D4 D5 D6 e E E1 E2 K L L1 P
ABC
VIEW B
2X
A4 0.004 (0.1)
M
ABC
2X
A3
2X
A2
84
2X
P 0.004 (0.1)
M
ABC
MCM72F6*MCM72F7 9
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
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MCM72F6*MCM72F7 10
MCM72F6/D MOTOROLA FAST SRAM

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